1. Field of the Invention
The present invention relates to integrated circuits (ICs) having self-test capability, and in particular, to mixed signal (i.e., digital and analog) ICs having self-test capability.
2. Description of the Related Art
As ICs have become increasingly sophisticated and complex (e.g., very large scale integration, or “VLSI”), the concept of design for testability (DFT) has become more important. The current economics of electronics manufacturing require that ICs be of very high quality before they are incorporated into products or systems. Simple functional testing, such as that provided by typical automated test equipment (ATE) is often inadequate. Accordingly, improvements in VLSI technology, e.g., in terms of gate density and increased clock speeds, have caused VLSI testing to become an integral part of the overall chip design. With the increased circuit complexity and higher operating speeds, external test equipment often fails to keep pace, thus preventing test and measurement under normal circuit operating conditions. As a result, built-in-self-test (BIST) has become an increasingly important and useful tool as part of DFT. This is particularly true and important for system-on-a-chip (SOC) designs and mixed signal ICs. In the case of mixed signal ICs, the BIST circuitry typically resides in the digital circuitry portion of the IC so that any performance impacts on the analog circuitry are minimized. However, notwithstanding the advantages of having BIST, as ICs become increasingly complex and dense, the overhead, in terms of additional circuitry associated with BIST becomes a new problem.
Accordingly, it would be desirable to have the advantages of BIST but without the disadvantages of the additional circuitry overhead associated with BIST.